1. Field of The Invention
The present invention relates generally to a semiconductor device formed on an insulating material and a manufacturing method thereof.
2. Description of The Prior Art
In recent years, the high integration of semiconductor integrated circuits, particularly dynamic random access memories (DRAMs), has progressed remarkably. However, the area of a memory cell tends to decrease as the integrated degree thereof increases, so that it is difficult to ensure sufficient cell capacity to prevent so-called soft-error caused by alpha rays radiated from package materials.
Therefore, a semiconductor device has been trying to form on a single crystal silicon film on an insulator film. This semiconductor device is called a Silicon-On-Insulator (SOI) element and promises to serve as a high-performance element which can operate at a high speed and with a low electric power consumption.
As shown in FIG. 15, a SOI MOSFET generally comprises: a semiconductor substrate 62; a buried oxide film 64 formed thereon; a single crystal silicon layer 66 of a first conductivity (e.g., p-type) formed thereon; diffusion layers 76a, 76b of a second conductivity (e.g., n-type) formed in the silicon layer 66 so as to serve as a source and a drain, the second conductivity being different from the first conductivity; a gate oxide film 69 formed on the silicon layer 66; and a gate electrode 70 formed on the gate oxide film 69. Using this SOI element, electron and hole pairs produced by alpha rays can be controlled so as to be located in the single crystal silicon layer (which will be also hereinafter referred to as a "SOI" layer), so that it is possible to greatly improve the soft-error immunity.
However, there are critical drawbacks caused by floating-body effect in that the SOI element (SOI MOSFET) has instabilities that drain breakdown voltage is lowered as shown in FIG. 16 and that the overshoot of output current is caused in switching operation as shown in FIGS. 17A-17F. That is, as shown in FIG. 16, the SOI MOSFET has a lower drain breakdown voltage than that of a MOSFET having the same gate length. In addition, when input voltages (gate pulses) shown in FIGS. 17A, 17C and 17E are applied to the gate electrode, output currents (drain currents) occur as shown in FIGS. 17B, 17D and 17F, respectively. In these output currents, overshoot occurs as shown by arrows in FIGS. 17B, 17D and 17F.
There have been provided methods for effectively preventing carriers produced by the impact ionization, which may cause the floating-body effect in such a SOI element, from accumulating in a channel region (e.g., for effectively preventing holes from accumulating in the case of a MOSFET of n-type SOI structure). For example, the aforementioned methods include: a method for forming a body contact; a method for providing a p-type silicon layer in a diffusion layer to directly connect the silicon layer to a channel region in the case of a n-type Si-MOSFET; and a method for forming, in a source region, a layer of a material (e.g., Si.sub.1-x Ge.sub.x) having a narrower bandgap than that of a channel region.
However, in the case of the body contact method, there are problems in that the area of a cell increases and that the sheet resistance of the region which connects the body-contact and the channel region can not be ignored as the size decreases. In the case of the method for providing the p-type silicon layer in the source region on the n-MOSFET, it is difficult to form the p-type silicon layer since the n.sup.+ layer and the p layer are stacked in the source. Moreover, there are problems in that the sheet resistance may increase, that the thickness of the n.sup.+ layer and the p layer can not be accurately controlled unless the heat treatment is suitably controlled, and that although it is desired to cause a hole-absorbing layer to approach a channel region by the lateral diffusion, such control can not be easily performed since the hole-absorbing layer reaches the channel region in some heat treatment conditions. There is also a problem in that it is not possible to prevent the thickness of the SOI layer from increasing in order to realize such a formation, so that it goes against the scale down trend such as the decrease of the SOI thickness for the scale down of the device.
In particular, as shown in FIG. 18A, in a case where a p-type silicon layer 75 is provided below a source region 76a so as to be directly connected to a channel region 66, there are problems in that the source region 76a and a drain region 76b are not symmetrically arranged with respect to a gate, and that it is not possible to apply a MOSFET of the aforementioned SOI structure to a transistor forming a memory cell of a DRAM. Furthermore, the reason why it can not be applied to a DRAM is as follows.
As shown in FIG. 19, a memory cell of a DRAM generally comprises a MOSFET 50 and a capacitor 55. A gate 51 of the MOSFET 50 is connected to a word wire WL, a source 52a is connected to a bit line BL, and a drain 52b is connected to one end of the capacitor 55. Furthermore, the other end of the capacitor 55 is grounded.
When a transistor shown in FIG. 18A is used as a transistor of the aforementioned memory cell, it can be clearly seen from the energy band diagram (see FIG. 18B) of a source region (p.sup.+ layer 75), a channel region (p-layer 66) and a drain region (n.sup.+ layer 76b) when a source potential is in a high level that electrons flow between the source and drain independent of a gate voltage V.sub.G. That is, when writing (when the source potential is in a high level), the control of the gate may be lost to cause the malfunction of the transistor shown in FIG. 18A, so that it is unsuitable for a device such as a DRAM wherein carriers move in both directions.
Thus, in a case where the p-type silicon layer 75 is arranged below the n-type source region 76a so as to be directly connected to the channel, when the source potential is in a high level, the pn junction between the channel region and the drain region is conducted, so that it can not be applied to many MOS devices including DRAMs.
In addition, in the case of the method for forming the region of a narrow-bandgap material in the source region, if the ion implantation is used to form the region of the narrow-bandgap material, the damage caused by the ion implantation into the diffusion layer region may cause problems with respect to the element characteristics.